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| ma2909/11 1 ds3577-3.4 preliminary information the ma2909/11 microprogram sequencer is fully compatible with the industry standard 2909a and 2911a components, and forms part of the gps 2900 series of devices. the series offers a building block approach to microcomputer and controller design, with each device in therange being expandable to permit efficient emulation of any microcode machine. the devices have tristate outputs and have an internal address register, with all internal registers changing state onlow to high clock transition. the 4-bit slice can cascade to any number of microwords. branch input for n-way branches is supported. additional features include:n 4-bit cascadable microprogram counter. n 4 x 4 file with stack counter supporting nestingmicrosubroutines. n zero input for returning to the zero microcode word. n individual or input for each bit for branching to highermicroinstructions (2909 only). the 2909 is a 4-bit wide address controller intended for sequencing through a series of microinstructions contained ina rom or prom. two 2909s may be interconnected to generate an 8-bit address (256 words), and three may be usedto generate a 12-bit address (4k words). the 2909 can select an address from any of four sources: 1) a set of external direct inputs (d);2) external data from the r inputs, stored in an internal register; 3) a four-word push/pop stack; or 4) a program counter register (which usually contains the last address plus one). the push/pop stack includes certain control lines so that it can efficiently execute nested subroutine linkages. each of thefour outputs can be ored with an external input for conditional skip or branch instructions, and a separate line forces the outputs to all zeroes. the outputs are three-state. the 2911 is an identical circuit to the 2909 except the four or inputs are removed and the d and r inputs are tied together. features n fully compatible with industry standard 2909a and2911a components n radiation hard cmos sos technology n high seu immunity n high speed / low power n fully ttl compatible april 1995 radiation hard microprogram sequencer ma2909/11
ma2909/112 figure 1: microprogram sequencer block diagram stk ptr ma2909/11 3 the 2909/2911 are cmos sos microprogram sequencers intended for use in high-speed microprocessor applications.the device is a cascadable 4-bit slice such that two devices allow addressing of up to 256 words of microprogram and three devices allow addressing of up to 4k words of microprogram. a detailed logic diagram is shown in figure 1. the device contains a four input multiplexer that is used to select either the address register, direct inputs, microprogramcounter, or file as the source of the next microinstruction address. this multiplexer is controlled by the s0 and s1 inputs. the address register consists of four d-type, edge triggered flip-flops with a common clock enable. when theaddress register enable is low, new data is entered into the register on the clock low-to-hlgh transition. the address register is available at the multiplexer as a source for the next microinstruction address the direct input is a 4-bit field of inputs to the multiplexer and can be selected as the next microinstruction address. on the 2911 the direct inputs arealso used as inputs to the register. this allows an n-way branch where n is any word in the microcode. the 2909/2911 contains a microprogram counter (pc) that is composed of a 4-bit incrementer followed by a 4bitregister. the incrementer has carry-in (c n ) and carry-out (c n + 4) such that cascading to larger word lengths is straight forward. the pc can be used in either of two ways. when theleast significant carry-in to the incrementer is high, the microprogram register is loaded on the next clock cycle withthe current y output word plus one (y + 1 pc). thus sequential microinstructions can be executed. if this least significant c n is low, the incrementer passes the y output word unmodified and the microprgram register is loaded withthe same y word on the next clock cycle (y pc). thus, the same microinstruction can be executed any number of timesby using the 4x4 file (stack). the file is used to provide return address linkage when executing microsubroutines. the file contains a built-in stack pointer (sp) which always points to the last file word written. this allows stack reference operations (looping) to be performed without a push or pop. the stack pointer operates as an up/down counter with separate push/pop and file enable inputs. when the file enableinput is low and the push/pop input is high, the push operation is enabled. this causes the stack pointer to increment and the file to be written with the required returnlinkage - the next microinstruction address following the subroutine jump which initiated the push. if the file enable input is low and the push/pop control is low, a pop operation occurs. this implies the usage of thereturn linkage during this cycle and thus a return from subroutine. the next low-to-hlgh clock transition causes thestack pointer to decrement. if the file enable is high, no action is taken by the stack pointer regardless of any other input. the stack pointer linkage is such that any combination of push, pop or stack references can be achieved. one microinstruction subroutine can be performed. since the stackis 4 words deep, up to four microsubroutines can be nested. the zero input is used to force the four outputs to the binary zero state. when the zero input is low all y outputsare low regardless of any other inputs (except oe). each y output bit also has a separate or input such that a conditional logic one can be forced at each y output. this allows jumping to different microinstructions on programmed conditions. the 2909/2911 feature three-state y outputs. these can be particularly useful in designs requiring external equipmentto provide automatic checkout of the microprocessor. the internal control can be placed in the high impedance state andpreprogrammed. multiplexer select codes table 1 lists the select codes for the multiplexer. the two bits applied from the microword register (and additional combinational logic for branching) determine which data source contains the address for the next microinstruction. thecontents of the selected source will appear on the y outputs. table 1 also shows the truth table for the output control and for the control of the push/pop stack. table 2 shows in detail the effect of s 0 , s 1 , fe and pup on the 2909. these four signals define the address that apears on the y outputs and what thestate of all the internal registers will be following the clock low-to-hlgh edge. in this illustration, the microprogram counter is assumed to contain initially some word j, the address register some word k, and the four words in the push/pop stack contain r a through r d . or1 xx h l zero x l hh oe h ll l h = high, l = low, z = high impedance table 1a: output control fe h ll zero x h l push-pop stack changeno change increment stack pointer, then push current pc on to stk0 pop stack (decrement stack pointer) h = high, l = low, x = irrelevant table 1b: synchronous stack control s 1 ll hh s 2 l h l h symbol pc ar stko d 1 source for y outputsmicroprogram counter address/holding register push-pop stack direct inputs table 1c: address selection y1 z l h source selected by s 0 s 1 ma2909/114 cycle n n + 1 n n + 1 n n + 1 n n + 1 n n + 1 n n + 1 n n + 1 n n + 1 n n + 1 n n + 1 n n + 1 n n + 1 s1 s0 fe pup l l l l - l l l h - l l h x - l h l l - l h l h - l h h x - h l l l - h l l h - h l h x - h h l l - h h l h - h h h x - pc j j + 1 j j + 1 j j + 1 j k + 1 j k + 1 j k + 1 j r a + 1 j r a + 1 j r a + 1 j d + 1 j d + 1 j d + 1 reg kk k k k k k k k k k k k k k k k k k k k k k k stk0 r a r b r a j r a r a r a r b r a j r a r a r a r b r a j r a r a r a r b r a j r a r a stk1 r b r c r b r a r b r b r b r c r b r a r b r b r b r c r b r a r b r b r b r c r b r a r b r b stk2 r c r d r c r b r c r c r c r d r c r b r c r c r c r d r c r b r c r c r c r d r c r b r c r c stk3 r d r a r d r c r d r d r d r a r d r c r d r d r d r a r d r c r d r d r d r a r d r c r d r d principal use end loop set-up loop continue end loop jsr ar jmp ar rts stack ref (loop) end loop jsr d jmp d 1 = high, 0 = low, x = irrelevant, assume c n = high note: stk0 is the location addressed by the stack pointer table 2: output and internal next-cycle register states for 2909/2911 table 3 (page 5) illustrates the execution of a subroutine using the 2909. the configuration of figure 2 is assumed. theinstruction being executed at any given time is the one contained in the microword register (wr). the contents of thewr also control (indirectly, perhaps) the four signals s0, s1, fe, and pup. the starting address of the subroutine is applied to the d inputs of the 2909 at the appropriate time. in the column on the left is the sequence of microinstructions to be executed. at address j+2, the sequence control portion of the microinstruction contains thecommand jump to subroutine at a. at the time t 2 , this instruction is in the wr, and the 2909 inputs are set-up to execute the jump and save the returnaddress. the subroutine address a is applied to the d inputs from the wr and appears on the y outputs. the first instruction of the subroutine, i(a), is accessed and is at theinputs of the wr. on the next clock transition, l(a) is loaded into the wr for execution, and the return address j + 3 is pushed on to the stack. the return instruction is executed at t 5 . table 4 is a similar timing chart showing one subroutine linking to a second, the latter consisting of only one microinstruction. y out j - j - j - k - k - k - r a - r a - r a - d - d - d - comment pop stackpush pc continue pop stack; use ar for address push pc; jump to address in arjump to address in ar jump to address in stk0; pop stack jump to address in stk0; push pc jump to address in stk0 pop stack; jump to address on d jump to address on d; push pc jump to address on d ma2909/11 5 execute cycle2909 inputs (from wr) internal registers 2909 output rom output contents of wr (instruction being executed) t 0 0 h xx j + 1 -- - - j + 1 i(j + 1) i(j) t 1 0 h xx j + 2 -- - - j + 2 jsr a i(j + 1) t 2 3l h a j + 3 -- - - a i(a) jsr a t 3 0 h xx a + 1 j + 3 -- - a + 1 i(a + 1) i(a) t 4 0 h xx a + 2 j + 3 -- - a + 2 rts i(a + 1) t 5 2l l x a + 3 j + 3 -- - j + 3 i(j + 3) rts t 6 0 h xx j + 4 -- - - j + 4 i(j + 4)i(j + 3) t 7 0 h xx j + 5 -- - - j + 5 i(j + 5)i(j + 4) t 8 t 9 s 1 , s 0 fepup d pc stk0 stk1 stk2 stk3 y (y) wr table 3: subroutine execution execute cycle t 0 t 1 t 2 t 6 t 7 t 3 t 4 t 5 address j - 1 j j + 1j + 2 j + 3 j + 4 -- - - - a a + 1a + 2 -- - - - - control memory microprogram sequencerinstruction -- - jsr a -- - - - - - i(a) - rts -- - - - - ma2909/116 t 0 0 h xx j + 1 -- - - j + 1 i(j + 1) i(j) t 1 0 h xx j + 2 -- - - j + 2 jsr a i(j + 1) t 2 3l h a j + 3 -- - - a i(a) jsr a t 3 0 h xx a + 1 j + 3 -- - a + 1 i(a + 1) i(a) t 4 0 h xx a + 2 j + 3 -- - a + 2 jsr b i(a + 1) t 5 2l l x a + 3 j + 3 -- - b rts jrs b t 6 0 h xx b + 1a + 3 j + 3 -- a+ 3 i(a + 3) rts t 7 0 h xx a + 4 j + 3 -- - a + 4 rts i(a + 3) t 8 2l l x a + 5 j + 3 -- - j + 3 i(j + 3) rts s 1 , s 0 fepup d pc stk0 stk1 stk2 stk3 y (y) wr address j - 1 j j + 1j + 2 j + 3 -- - - a a + 1a + 2 a + 3 a + 4 -- - - b - control memory t 9 0 h xx j + 4 -- - - j + 4 i(j + 4)i(j + 3) table 4: two nested subroutines microprogram sequencerinstruction -- - jsr a -- - - - - - jsr b - rts -- - - rts - execute cycle t 0 t 1 t 2 t 9 t 3 t 4 t 5 t 7 t 8 t 6 execute cycle2909 inputs (from wr) internal registers 2909 output rom output contents of wr (instruction being executed) ma2909/11 7 dc characteristics and ratings parameter min max units supply voltage -0.5 7 v input voltage -0.3 v dd +0.3 v current through any pin - 20 ma operating temperature -55 125 c storage temperature -65 150 c note: stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions, or atany other condition above those indicated in the operations section of this specification, is not implied. exposure to absolute maximum rating conditions for extended periodsmay affect device reliability. table 5: absolute maximum ratings subgroup definition 1 static characteristics specified in table 7 at +25c 2 static characteristics specified in table 7 at +125c 3 static characteristics specified in table 7 at -55c 7 functional characteristics at +25c 8a functional characteristics at +125c 8b functional characteristics at -55c 9 switching characteristics specified in tables 8, 9 and 10 at +25c 10 switching characteristics specified in tables 8, 9 and 10 at +125c 11 switching characteristics specified in tables 8, 9 and 10 at -55c table 6: definition of subgroups symbolv oh v ol v ih v il i ih i il i ozh i ozl i dd parameteroutput high voltage output low voltage input high level (note 1) input low level (note 1) input high current input low current tristate high current tristate low current power supply current conditionsv dd = min., i oh = -2.6ma, v in = v ih or v il v dd = max., i ol = 16 ma, v in = v ih or v il guaranteed input logical high voltage for all inputsguaranteed input logical low voltage for all inputs v in = v dd (note 3) v in = v ss (note 3) v o = v dd (note 3) v o = v ss (note 3) units vv v v aa a a ma max. - 0.5 - 0.8 10 -10 50 -50 10 min. v dd -0.5 - v dd /2 -- - - - - notes:mil-std-883, method 5005, subgroups 1, 2, 3. 1. these input levels provide no guaranteed noise immunity and should only be static tested in a noise-free environment. 2. v dd = 5v 10%, over full operating temperature range. 3. guaranteed but not tested at low temperatures. table 7: dc operating characteristics ma2909/118 table 8: cycle time and clock charcteristics time minimum clock low time 15 minimum clock high time 15 c n + 4 4035 30 25 40 -- 4545 45 set-up time 1010 20 20 15 20 20 20 25 hold time 10 75 10 50 0 0 0 from input re r i pup fe c n d i or i s 0 , s 1 zero notes:1. cl < 50pf 2. rl 3 680 w 3. rl 3 680 w , measured 0.5v change in output level table 9: maximum combinational propogation delays table 10: guaranteed set-up and hold times (all in ns) all times in ns across full voltage and temperature range.mil-std-883, method 5005, subgroups 9, 10 and 11. figure 2 y 3530 20 - 3525 25 40 40 50 from input d 1 s 0 , s 1 or i c n zero oe low (enable) (note 2) oe high (disable) (note 3) clock: s 1 s 0 = lh clock: s 1 s 0 = ll clock: s 1 s 0 = hl ma2909/11 9 d w a e b z h a 1 15 m e c e 1 seating plane 1 14 28 15 figure 3: 28-lead ceramic dil (solder seal) - package style c package outlines ref millimetres inches min. nom. max. min. nom. max. a - - 5.715 - - 0.225 a1 0.38 - 1.53 0.015 - 0.060 b 0.35 - 0.59 0.014 - 0.023 c 0.20 - 0.36 0.008 - 0.014 d - - 36.02 - - 1.418 e - 2.54 typ. - - 0.100 typ. - e1 - 15.24 typ. - - 0.600 typ. - h 4.71 - 5.38 0.185 - 0.212 me - - 15.90 - - 0.626 z - - 1.27 - - 0.050 w - - 1.53 - - 0.060 xg404 28 vcc 27 cp 26 pup 25 fen 24 c n+4 23 c n 22 oen 21 y3 20 y2 19 y1 18 y0 17 s1 16 s0 15 zeron 1 ren 2 r3 3 r2 4 r1 5 r0 6 or3 7 d3 8 or2 9 d2 10 or1 11 d1 12 or0 13 d0 14 gnd top view ma2909/1110 e b e d l a q c pin 1 s e2 figure 3: 28-lead dual flatpack (solder seal) - package style c ref millimetres inches min. nom. max. min. nom. max. a - - 2.97 - - 0.117 b 0.381 - 0.482 0.015 - 0.019 c 0.076 - 0.152 0.003 - 0.006 d 18.08 - 18.49 0.712 - 0.728 e 12.50 - 12.9 0.492 - 0.508 e2 9.45 - 9.85 0.372 - 0.388 e 1.143 - 1.40 0.045 - 0.055 l 8.00 - 9.27 0.315 - 0.365 q 0.66 - - 0.026 - - s - - 1.14 - - 0.045 xg543 ma2909/11 11 radiation tolerancetotal dose radiation testing for product procured to guaranteed total dose radiation levels, each wafer lot will be approved when all sample devices from each lot pass the total dose radiation test. the sample devices will be subjected to the total dose radiation level (cobalt-60 source), defined by the orderingcode, and must continue to meet the electrical parameters specified in the data sheet. electrical tests, pre and post irradiation, will be read and recorded. gec plessey semiconductors can provide radiation testing compliant with mil-std-883 test method 1019, ionizing radiation (total dose). total dose (function to specification)* 3x10 5 rad(si) transient upset (stored data loss) 5x10 10 rad(si)/sec transient upset (survivability) >1x10 12 rad(si)/sec neutron hardness (function to specification) >1x10 15 n/cm 2 single event upset** 1x10 -10 errors/bit day latch up not possible * other total dose radiation levels available on request** worst case galactic cosmic ray upset - interplanetary/high altitude orbit table 11: radiation hardness parameters ordering information for details of reliability, qa/qc, test and assembly options, see manufacturing capability and quality assurance standards section 9. unique circuit designator sr q radiation hard processing 100 krads (si) guaranteed 300 krads (si) guaranteed radiation tolerance c n f ceramic dil (solder seal)naked die flatpack (solder seal) package type qa/qci process (see section 9 part 4) test process (see section 9 part 3) assembly process (see section 9 part 2) l c d eb s rel 0rel 1 rel 2 rel 3/4/5/stack class bclass s reliability level max2911xxxxx max2909xxxxx ma2909/1112 headquarters operationsgec plessey semiconductors cheney manor, swindon, wiltshire, sn2 2qw, united kingdom. tel: (01793) 518000 fax: (01793) 518411 gec plessey semiconductors p.o. box 660017, 1500 green hills road, scotts valley, california 95067-0017, united states of america. tel: (408) 438 2900 fax: (408) 438 5576 customer service centres? france & benelux les ulis cedex tel: (1) 64 46 23 45 fax: (1) 64 46 06 07 ? germany munich tel: (089) 3609 06-0 fax: (089) 3609 06-55 ? italy milan tel: (02) 66040867 fax: (02) 66040993 ? japan tokyo tel: (03) 5276-5501 fax: (03) 5276-5510 ? north america scotts valley, usa tel: (408) 438 2900 fax: (408) 438 7023 ? south east asia singapore tel: (65) 3827708 fax: (65) 3828872 ? sweden stockholm tel: 46 8 702 97 70 fax: 46 8 640 47 36 ? taiwan, roc taipei tel: 886 2 5461260 fax: 886 2 7190260 ? uk, eire, denmark, finland & norway swindon, uk tel: (01793) 518527/518566 fax: (01793) 518582 these are supported by agents and distributors in major countries world-wide.? gec plessey semiconductors 1995 publication no. ds3577-3.3 march 1995 technical documentation - not for resale. printed in united kingdom. this publication is issued to provide information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor tobe regarded as a representation relating to the products or services concerned. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product orservice. the company reserves the right to alter without prior knowledge the specification, design or price of any product or service. information concerning possible methods of use is provided as a guideonly and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user's responsibility to fully determine the performance and suitab ility ofany equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to the company's conditions of sale, which are available on request. www .zarlink.com ! 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